Test MP+dmb.sy+ctrl-ctrl-rfi-[fr-rf]-addr

AArch64 MP+dmb.sy+ctrl-ctrl-rfi-[fr-rf]-addr
"DMB.SYdWW Rfe DpCtrldR DpCtrldW Rfi FrLeave RfBack DpAddrdR Fre"
Cycle=Rfi FrLeave RfBack DpAddrdR Fre DMB.SYdWW Rfe DpCtrldR DpCtrldW
Relax=
Safe=Rfi Rfe Fre DMB.SYdWW DpAddrdR DpCtrldW DpCtrldR [FrLeave,RfBack]
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr Rf
Orig=DMB.SYdWW Rfe DpCtrldR DpCtrldW Rfi FrLeave RfBack DpAddrdR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X3=z; 1:X5=a; 1:X10=x;
2:X1=a;
}
 P0          | P1                   | P2          ;
 MOV W0,#1   | LDR W0,[X1]          | MOV W0,#2   ;
 STR W0,[X1] | CBNZ W0,LC00         | STR W0,[X1] ;
 DMB SY      | LC00:                |             ;
 MOV W2,#1   | LDR W2,[X3]          |             ;
 STR W2,[X3] | CBNZ W2,LC01         |             ;
             | LC01:                |             ;
             | MOV W4,#1            |             ;
             | STR W4,[X5]          |             ;
             | LDR W6,[X5]          |             ;
             | LDR W7,[X5]          |             ;
             | EOR W8,W7,W7         |             ;
             | LDR W9,[X10,W8,SXTW] |             ;
Observed
    y=1; x=1; a=2; 1:X9=1; 1:X7=1; 1:X6=2; 1:X0=0;